The present invention relates generally to semiconductor device fabrication and, more particularly, to electrostatic discharge (ESD) circuits for protecting an Input/Output (I/O) signal pad in radio frequency and other high frequency signal applications, as well as methods for providing ESD protection and design structures for an ESD protection circuit.
Modern electronics achieve high levels of functionality in small form factors by integrating multiple functions onto a single chip. A common fabrication process that allows high levels of integration at a relatively low cost is Complementary Metal-Oxide-Semiconductor (CMOS). CMOS processes build a combination of p-type and n-type metal-oxide-semiconductor field-effect transistors (MOSFETs) to implement logic gates and other types of digital circuits.
Chips may be exposed to electrostatic discharge (ESD) events leading to potentially large and damaging currents within the integrated circuit. Increasing integration densities and performance demands on CMOS chips have resulted in reduced device dimensions. The reduction in dimensions has increased the susceptibility of integrated circuits to ESD events. Manufacturers, assemblers, and users of integrated circuits must take precautions to avoid unintentionally causing ESD events. For example, ESD prevention can be incorporated into the integrated circuit and may include special design techniques for I/O pins and pads to prevent damage to the chip during handling from the time that the chip is manufactured until the time that the chip is installed on a circuit board.
High frequency circuit applications require ESD protection circuits that can handle sufficient ESD current levels but that do not add significant parasitic capacitance to the signal pad. Semiconductor Controlled Rectifier (SCR) circuits, which offer both low capacitance and high failure currents, may be used to provide ESD protection in CMOS applications. SCR devices used for ESD protection typically require a trigger circuit in order to respond to ESD events at a voltage that is sufficiently low to protect integrated circuits of CMOS chips. One such trigger circuit that provides both fast transient turn on and low trigger voltages for an SCR is a resistor-capacitor (RC) trigger circuit.
Therefore, improved RC-trigger circuits for an SCR, as well as methods, and design structures for SCR RC-trigger circuits are needed for protecting integrated circuits against ESD events.